The present invention generally relates to data transmission circuits and more specifically to cross-point switches.
A cross-point switch is an array of cross-points wherein one of N inputs is selectively connected to one of M outputs. Any or all of the interconnections may change for each cycle of operation. The cross-point switch must be capable of handling a new selection without disturbing or interrupting the present selection until an update command is received. Although each input is only connected to one output and each output only has one input data, the cross-point switch also has the capability of connecting one input to more than one output simultaneously and if an OR function is acceptable, a single output may be connected to more than one input. For sake of clarity, the explanation within this patent will be described only with respect to each input being connected to only one output and each output having only one input connected thereto.
In prior art cross-point switches, each column or data out-line included a next state register NSR and a present state register CSR which are activated by a clock CLK. Each cross-point included a decoder for decoding the present state and the output of the decoder was combined in an AND gate with the specific data input line to provide an output on the data out-line. Thus the registers in combination with the decoder of the cell provided the data in and data out decoder. The basic structure is described in FIGS. 1 and 2 wherein four adjacent cross-points are illustrated in FIG. 2.
In the prior art structure assuming for example, that there are 32 possible inputs, each register would have to have five select lines, if only the true values are used by the decoders, or ten lines, if the true and negative complement are used. Using the true and complement select lines allows the decoder to consist of a five input gate. If there are also 32 outputs using ten select lines per output would require 320 select lines running the length of the cross-point switch. Although the prior art of FIGS. 1 and 2 are illustrated as an array, in one implementation by Sierra Semiconductor 32.times.32 cross-point switch SC 11320, each column including decoders and AND gates represents a 32:1 multiplexer. Thus, for 32 outputs, there are 32 multiplexers and 32 latches or registers. A separate decoder and bus is provided to read the information in the 32 latches.
Thus it is an object of the present invention to provide a cross-point switch which requires less area.
It is another object of the present invention to provide a cross-point switch which is more compact.
These and other objects are achieved by providing the function of the next and present registers of the prior art at the cross-points and providing the decoding logic external at the cross-points. Each cross-point includes a first and second storage devices with the next cycle information being stored in the first storage device and transferred to the second storage device which has the present cycle information. The output of the second storage device is used in combination with a second controlling input to control the switch or logic at a cross-point. The two inputs to the cross-point logic are an address or state select and input data.
In one embodiment, the cross-point state is stored in these storage devices. The decoders activate and store in the first storage devices the next interconnect configuration for that cross-point which is then transferred in a second cycle to the second storage device. The output of the second storage device is provided to the switch logic and combined with the data in line to provide an output on the data out-line.
In another embodiment, the first storage device stores the next cycle data and is transferred upon appropriate signal to the second storage device which contains the present cross-point data. The output of the second storage device is combined with a decoder signal for example, the input decode, so as to connect the logic combination thereof to the data out-line. Appropriate clock or transfer signals are provided to store and transfer information between the storage devices at each of the cross-points. Although the present and next input data are stored at each of the cross-points, only the decoded cross-points are completed.
The cross-point switch may be programmed by individually activating the input decodes while the output decoders selectively determine the cross-point state for each output line with respect to the individual input, or the output decoders can individually select the output lines while the input decoders selectively determine the cross-point state for each input line with respect to the individual output.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.